1. Field of the Invention
The present invention relates generally to semiconductor technology, and particularly to a method for forming an interconnect structure.
2. Description of Prior Art
The semiconductor manufacturing technology is a kind of planar manufacturing process. Large amounts of complex devices of various kinds are formed on a same substrate, and these devices are connected with each other so that they have complete electronic functions. During the manufacturing process, a large amount of grooves is formed on the substrate, so that a metal interconnect structure can be formed by filling a metal material into the grooves.
With the continuous demand for high level of integration and high-performance of very large scale integrated circuits, semiconductor technology is developing in a direction of smaller feature size, and the operation speed of chips is greatly affected by the resistance-capacitance (RC) delay caused by metal interconnects. To improve the performance of the integrated circuit, on one hand, Cu which has advantages such as low resistivity, high resistance to electromigration can replace Al as metal interconnects in the semiconductor to lower the resistance of metal interconnects.
On the other hand, the use of a low dielectric constant (Low K) inter-dielectric layer or a very Low K inter-dielectric layer as inter-metal dielectric (IMD) can effectively decrease the capacitance. Cu interconnect technology associated with IMD made of Low K materials is currently the most popular combination. It can effectively improve the resistive-capacitive effects, and certainly will become one of the standard interconnects technologies for next generation of semiconductor technology.
A schematic flow chart of a conventional method for forming an interconnect structure is shown in FIG. 1, which includes providing a semiconductor substrate having a dielectric layer formed thereon, the dielectric layer comprising a barrier layer, a Low K inter-dielectric layer, a cap layer and a hard mask layer sequentially formed thereon (S101); etching the dielectric layer on the semiconductor substrate to form a groove (S103); depositing Cu into the groove until Cu fills in the groove and covers the hard mask layer at both sides of the groove (S105); planarizing Cu and the dielectric layer by using chemical mechanical polishing technology until the Low K inter-dielectric layer is exposed (S107).
However, the RC delay of the interconnect structure formed by the conventional method is large so that a satisfactory performance of the semiconductor devices cannot be obtained.